ASICE can start with just an idea or ‘wish list’ of yours.

It's then developed into a chip specification and list of circuit requirements.

A foundry is chosen based on circuit requirements.

Schedule and cost estimate are generated with key milestones marked.

The circuit schematic is designed that will meet your requirements.  Previously designed cells can be incorporated into the design where appropriate to save time and money.

Circuit is fully simulated using state-of-the-art models and the latest process parameters for the chosen foundry.

A design review is held with customer to review expected performance vs the earlier generated chip specifications.  Any level of desired customer review formality can be accommodated.

ASICE will layout the integrated circuit. Prior designed cells are incorporated into the layout where appropriate.

Verification software is used to see that the layout exactly matches the circuit schematic.

Parasitic capacitances are extracted from layout, circuit schematic is back annotated and re-simulated.

Complete chip level LVS and DRCs are run.

A design review is held with customer to review the revised expected performance. Interface documents are presented.  Color plots of layout up to 3 feet wide can be provided.  Any level of customer review formality can be accommodated.

Layout is then submitted to foundry for a prototype run.

Sample die are wirebonded into packages for testing.

Packaged parts are delivered to customer for evaluation.

After successful customer evaluation, a full lot of parts can then be started.